1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device. More specifically, the invention relates to test terminal arrangement in the semiconductor integrated circuit device and a test terminal arrangement method in the semiconductor integrated circuit.
2. Description of Related Art
As a master-slice type semiconductor device, a configuration as shown in FIG. 2 is disclosed in Patent Document 1. A peripheral circuit region of the semiconductor device includes a first cell 40 having a test terminal 10, second cells 50-1 to 50-2 which are respectively connected to signal terminals 20 and 30 and each of which inputs/outputs a signal, third cells 60-1 to 60-2 which respectively include power supply terminals 61 and 62, a fourth cell 70-1 which is not connected to the signal terminal 20, and a fifth cell 80-1 provided at one of four corners. A potential fixing circuit 26 (36) that fixes potentials at input signal wirings arranged on n cells (n<N) of N second cells is provided. A control signal wiring 42 provided from the test terminal along the peripheral circuit region is connected to a control terminal of the potential fixing circuit 26 (36), and a plurality of buffers 100 are connected midway between the test terminal and the control terminal of the potential fixing circuit 26 (36). A delay and wave-form blunting of a control signal which turns on/off the circuit that fixes the potentials of the signal input wirings is thereby canceled.
As a chip corner part cell, Patent Document 2, for example, discloses a configuration in which the shape of an input/output circuit cell at a chip corner part is set to a right triangle having one 45-degree angle. With this configuration, the area of the chip corner part can be effectively utilized, and the number of input/output terminals can be increased.
With respect to a go round wiring for testing, repeaters (buffers) inserted in the go round wiring which will be described later, a description of Patent Document 3, for example, is referred to.
[Patent Document 1] JP Patent Kokai Publication No. JP-P-2000-260880A (FIG. 1)
[Patent Document 2] JP Patent Kokai Publication No. JP-A-04-93047 (FIG. 2)
[Patent Document 3] JP Patent Kokai Publication No. JP-P-2004-260093A (FIG. 9)